CAM config register.
| CAM_STOP_EN | Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. |
| CAM_VSYNC_FILTER_THRES | Filter threshold value for CAM_VSYNC signal. |
| CAM_UPDATE | 1: Update Camera registers, will be cleared by hardware. 0 : Not care. |
| CAM_BYTE_ORDER | 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. |
| CAM_BIT_ORDER | 1: invert data byte order, only valid in 2 byte mode. 0: Not change. |
| CAM_LINE_INT_EN | 1: Enable to generate CAM_HS_INT. 0: Disable. |
| CAM_VS_EOF_EN | 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. |
| CAM_CLKM_DIV_NUM | Integral Camera clock divider value |
| CAM_CLKM_DIV_B | Fractional clock divider numerator value |
| CAM_CLKM_DIV_A | Fractional clock divider denominator value |
| CAM_CLK_SEL | Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. |